1. Field of the Invention
The present invention relates to a semiconductor memory, and in particular to a random access memory.
2. Description of the Related Art
Conventionally, the control of reading and writing in a random access memory has generally been limited to either a read mode or write mode for each cycle, and as a mode for carrying out reading and writing within the same time period, either "read-modify-write" or a dual-port random access memory using serial ports has been employed.
FIG. 1 is a block diagram showing a random access memory of the prior art, and FIG. 2 is a "read-modify-write" timing chart for the random access memory shown in FIG. 1.
As external inputs, a random access memory includes power pins (VDD and GND), a row address strobe signal pin 51 (/RAS), a column address strobe signal pin 52 (/CAS), a plurality of address pins 53, write enable signal pin 54 (/WE), output enable signal pin 55 (/OE), data input pin 56 (DIN), and data output pin 57 (DOUT); these pins determining operation modes and effecting input and output of data. The internal circuits are mainly composed of memory cell matrix 61, address judgment circuit 62, row address designation circuit 63, column address designation circuit 64, read/write control circuit 65, input data buffer circuit 66, and output data buffer circuit 67. Here, the slash included in labels such as "/RAS" indicates activation at low level.
The read-modify-write operation in the random access memory shown in FIG. 1 will next be explained with reference to FIG. 2.
When row address strobe signal pin 51 becomes active at time t.sub.1, the data of outside address signal 53 at this time is taken in by address judgment circuit 62, and a row address is designated by row address designation circuit 63. When column address strobe signal pin becomes active at time t.sub.2, the data of outside address signal 53 at this time is taken into address judgment circuit 62 in the same way as for the row, and a column address is designated by column address designation circuit 64.
In the case of a read-modify-write operation, the enabling of output enable signal/OE at this point in time t.sub.2 causes the data of the memory cell designated by the row and column addresses to pass through the input/output bus 68 and be outputted by way of data output pin 57. The subsequent enabling of write enable signal/WE designates a write operation, which in turn causes the data of data input pin 56 to be taken in by input buffer circuit 66 and written to the memory cell of the address designated from input/output bus 68. On the other hand, output buffer circuit 67 activates read/write control signal 65 and halts the output of output data.
FIG. 3 is a block diagram of a dual-port random access memory of the prior art, and FIG. 4 is a timing chart of the dual-port random access memory shown in FIG. 3.
As shown in FIG. 3, the dual-port random access memory is provided with, in addition to an ordinary random access memory, serial port read/write control circuit 72, serial port enable signal 73 (/SE) as outside input, serial port clock signal pin 74 (/SC), serial port data input/output pin 71 (SIO), and serial port data storage buffer circuit 75. These components determine the mode of operation and effect the input and output of data.
The operation of the dual-port random access memory will next be described with reference to FIG. 4.
As for the random access unit described hereinabove, when row address strobe signal pin 51 is activated at time t1, the data of outside address signal 53 at this time is taken into address judgment circuit 62 and a row address is designated by row address designation circuit 63. When column address strobe signal pin 52 becomes active at time t.sub.2, the data of outside address signal 53 at this time is taken into address judgment circuit 62 in the same way as for the row and a column address is designated by column address designation circuit 64.
In the case of a dual-port random access memory, the enabling of outside signal SE at time t.sub.1 enables the serial port, and the data of the memory cell designated by the row and column addresses are sent bit by bit from serial port input/output pin 71 to serial port data storage buffer circuit 75 during the activation of serial port clock signal 72; while in the case of a serial-read operation, the data of the memory cell designated by the row and column addresses are sent to data storage buffer circuit 75 and outputted bit by bit from serial data input/output pin 71 during the activation of serial port clock signal 72. By providing serial port data storage buffer circuit 75 and storing data in this buffer, data can be transferred using serial port input/output pin 71 asynchronously with the random access section, thereby making it possible to write in the serial port section while reading in the random access section, or to read in the serial port section while writing in the random access section.
In the case of a read-modify-write operation, after ending a normal read operation and outputting data from a memory cell from the output pin, a write operation is performed and new data are written to the same address. However, not only does this operation entail the time for the read operation and write operation in addition to the time for determining address, but the permissible address for a read operation and write operation during the same time period is limited to the same address.
On the other hand, when effecting a read operation and write operation simultaneously by a dual-port random access memory during the same time period, either data of a memory cell are temporarily stored in a serial port data storage buffer of the serial port section by data transfer, or stored data are transferred to a memory cell in a data transfer cycle, and this not only complicates a simultaneous read operation and write operation to any address, but also prevents a read operation or write operation during the same time period in page mode using the serial port section.